1. Field of the Invention
The invention relates to a solid-state image pickup device having a one-dimensional or two-dimensional pixel signal adding means and a camera using such a solid-state image pickup device.
2. Related Background Art
Hitherto, as a method of adding pixel signals in a solid-state image pickup device, for example, there is a method disclosed in JP-A-2000-106653 as a Japanese Patent. FIG. 14 shows a conventional example showing a construction in which signals of 2-dimensional pixels are added by a (2H line memory+2H line adder) 206. A specific circuit construction of the signal adder circuit portion is shown in FIG. 15. For example, the pixel signals are outputted to output lines 108-1 and 108-2 and stored into capacitors C2-1, C3-1, and the like through MOS switches 123-1 and 126-1, after that, the MOS switches 123-1 and 126-1 are turned on, and an addition (average) output is obtained through a wiring 117-1.
As mentioned above, in the conventional example, input units of the pixel adding means are connected in common to the output line for executing a normal output (non-adding).
However, in such a construction of the common output line, the normal output burdens the signal lines more than in the case where there are no adding means, causing a delay of output time. The example of FIGS. 14 and 15 will be described hereinbelow. In the diagrams, the normal (non-adding) output is outputted to the wiring 117-1. In this instance, since there are MOS switches 123-1, 126-1, and 143-1 of the signal adder circuit, a floating capacitance is added. In JP-A-2000-106653, a value of the floating capacitance, which is added, increases with an increase in number of switches, the floating capacitance exercises a large influence in dependence on the degree of the addition, and the occurrence of a decrease in signal gain, a reduction in response speed, and the like is presumed.